Current Issue : July-September Volume : 2026 Issue Number : 3 Articles : 5 Articles
Very Large-Scale Integration (VLSI) technology has been crucial to the rapid advancement of contemporary electronics because it has made it possible for small, fast, and energy-efficient systems to be employed in artificial intelligence, biomedical devices, communication, and computation. Innovation in devices from the micrometer scale to the present nanoscale and new atomic-scale technologies has been fueled by ongoing improvements in materials, fabrication techniques, system architectures, and design methodology. This paper offers a thorough summary of recent developments in VLSI design and technology, with particular attention on heterogeneous chiplet-based technologies, low-power architecture, high-performance computing systems, hardware that is neuromorphic and AI-oriented, and 3D integrated circuits. A thorough discussion is held regarding the main issues of manufacturing complexity, power management, thermal reliability, and scaling. Future themes are highlighted in the assessment, including spintronics, quantum computing, AI-driven design automation, 3D/2.5D integration, beyond-CMOS devices, and sustainable semi-conductor technologies....
With the advent of electric vehicles, the demand for non-destructive inspection methods for battery evaluation has increased. Among various requirements, achieving high-frame-rate performance is particularly critical for rapid inspection in end-user systems. However, image delay, which increases with frame rate, has emerged as a significant challenge due to inherent limitations in sensor design. As a result, extensive research has been conducted to improve image lag performance. In this study, we conducted an in-depth analysis of the fundamental causes of image lag in image sensors. Based on these findings, we fabricated a novel sensor with a reset transistor separate from the readout transistor used for data transfer. This approach effectively increased the reset current of the photodiode, significantly reducing image lag. The transistor material used in this study was InGaZnO, which showed a significant improvement in image lag compared to conventional methods. By introducing a dedicated reset transistor, the allowable reset current of the PIN diode was increased by a factor of 100 compared to the ROIC-limited condition, resulting in a significant reduction in image lag from 3.8% (STS) to 0.9% (DTS) under high-frame-rate operation. This research provides a theoretical basis for proposing various new X-ray digital image sensor structures....
The exceptional adjustability and ambipolar behavior of graphene offer significant potential for next-generation optoelectronics, where the conductivity of graphene is primarily modulated by the interface field of heterojunction. However, interface defects, which are inevitably introduced during fabrication, severely limit the effectiveness of gate voltage modulation. Although the layer-by-layer transfer method can effectively enhance conductivity, it also raises the carrier concentration and impairs the symmetry of ambipolar characteristics. This work presents a stacked multi-gate graphene transistor in which synergistic modulation enables efficient regulation of channel conductivity while maintaining low carrier concentration. Simulations are carried out to analyze how mobility, doping concentration, and the number of stacking layers influence the modulation of conductivity. Experimentally, a three-layer stacked graphene structure with distributed source and drain electrodes is fabricated. The device exhibits pronounced ambipolar transfer characteristics and demonstrates a clear improvement in transconductance compared to its conventional one-layer graphene counterpart. This research offers a feasible design strategy for high-performance, vertically integrated graphene-based electronic devices....
This paper presents a novel Double Buried-Window Junctionless Field-Effect Transistor (DBW-FET) designed for high-sensitivity, label-free biosensing applications. The proposed device integrates two buried windows, one N-type and one P-type, beneath the active channel within the buried oxide layer, along with two nanocavities serving as biomolecular recognition sites. The dual buried windows form two depletion regions that enhance electrostatic coupling, suppress short-channel effects, and improve biomolecular sensitivity. Numerical simulations using Silvaco TCAD Atlas were performed to investigate device performance under various biomolecular binding conditions. Results show that the DBW-FET exhibits higher drain current, lower subthreshold swing, and improved sensitivity compared with a conventional junctionless FET (C-FET). Furthermore, a machinelearning- assisted optimization framework employing Gaussian Process Regression (GPR) and Bayesian Optimization (BO) was implemented to identify optimal buried window parameters. The optimized design achieved a 20–25% improvement in current sensitivity while maintaining low leakage. These findings demonstrate that the proposed DBW-FET offers a promising and Complementary Metal-Oxide-Semiconductor (CMOS)-compatible architecture for next-generation nanoscale biosensors....
The increasing complexity of modern Very Large-Scale Integration (VLSI) circuits, combined with unavoidable variations in physical and manufacturing parameters, poses significant challenges for accurate and efficient circuit simulation. Parametric model order reduction (PMOR) provides a viable solution by enabling the construction of compact reduced-order models that remain valid across a prescribed parameter space. However, the computational cost of generating such models can become prohibitive for large-scale circuits, particularly when high-fidelity projection subspaces are required. In this work, we present an efficient PMOR framework based on the Asymmetric Extended Krylov Subspace (AEKS). The proposed approach exploits structural sparsity imbalances between system matrices to guide the subspace expansion toward computationally favorable directions, thereby significantly reducing the cost of repeated linear system solves. By integrating AEKS within a concatenation-of-basis PMOR strategy, this method enables the rapid construction of accurate parametric reduced-order models for large-scale circuit systems. The proposed AEKS-PMOR framework is evaluated on industrial power distribution network benchmarks, where it demonstrates substantial reductions in model construction time compared to conventional EKS-based PMOR, while maintaining high approximation accuracy over the entire parameter space....
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